Multiplexador 4:1 para mais de 1 bit

É possível implementar o multiplexador 4:1 para mais de um 1 bit de três formas diferentes: utilizando o cascateamento de multiplexadores 4:1 de 1 bit, através da estrutura when…else e por meio da estrutura with…select.

Utilizando o cascateamento de multiplexadores 4:1

Primeiramente vamos recordar a descrição do multiplexador 4:1 de 1 bit:

library ieee;
use ieee.std_logic_1164.all;

entity mux_logic is
    port(
        a, b, c, d  :   in std_logic;
        s1, s0      :   in std_logic;
        x           :   out std_logic
    );
end mux_logic;

architecture dataflow of mux_logic is
begin
    x <= (a and (not s1) and (not s0)) or (b and (not s1) and s0) or (c and s1 and (not s0)) or (d and s1 and s0); 
end dataflow;

Após isso, podemos fazer o cascateamento dos multiplexadores de 1 bit. A largura dos dados do multiplexador foi declarado como um genérico para permitir a reusabilidade do código.

library ieee;
use ieee.std_logic_1164.all;

entity mux_4x1_portmap is
    generic(
        N : integer := 32
    );
    port(
          a, b, c, d  :   in std_logic_vector (N-1 downto 0);
          s1, s0      :   in std_logic;
          x           :   out std_logic_vector (N-1 downto 0)
    );
end mux_4x1_portmap;

architecture arch of mux_4x1_portmap is
    component mux_logic is
        port(
            a, b, c, d  :   in std_logic;
            s1, s0      :   in std_logic;
            x           :   out std_logic
        );
    end component;
begin
    GENERATE_MUX : for index in 0 to N-1 generate
        mux0 : mux_logic port map (a=>a(index), b=>b(index), c=>c(index), d=>d(index), s1=>s1, s0=>s0, x=>x(index));
    end generate GENERATE_MUX;
end arch;

Utilizando a estrutura when…else

library ieee;
use ieee.std_logic_1164.all;

entity mux_when_else is
  generic(
        N : integer := 32
    );
  port(
        a, b, c, d  :   in std_logic_vector (N-1 downto 0);
        s1, s0      :   in std_logic;
        x           :   out std_logic_vector (N-1 downto 0)
  );
end mux_when_else; 

architecture arch of mux_when_else is
    signal sel : std_logic_vector (1 downto 0);
begin
    sel <= s1 & s0;
    x <= a when sel="00" else
         b when sel="01" else
         c when sel="10" else
         d;
end arch;

Utilizando a estrutura with…select

library ieee;
use ieee.std_logic_1164.all;

entity mux_with_select is
  generic(
        N : integer := 32
    );
  port(
        a, b, c, d  :   in std_logic_vector (N-1 downto 0);
        s1, s0      :   in std_logic;
        x           :   out std_logic_vector (N-1 downto 0)
  );
end mux_with_select; 

architecture arch of mux_with_select is
    signal sel : std_logic_vector (1 downto 0);
begin
    sel <= s1 & s0;
    with sel select
        x <= a when "00",
             b when "01",
             c when "10",
             d when others;
end arch;