Multiplexador 4:1

library ieee;
use ieee.std_logic_1164.all;

entity mux_logic is
    port(
        a, b, c, d  :   in std_logic;
        s1, s0      :   in std_logic;
        x           :   out std_logic
    );
end mux_logic;

architecture dataflow of mux_logic is
begin
    x <= (a and (not s1) and (not s0)) or (b and (not s1) and s0) or (c and s1 and (not s0)) or (d and s1 and s0); 
end dataflow;

library ieee;
use ieee.std_logic_1164.all;

entity mux_when_else is
  port(
        a, b, c, d  :   in std_logic;
        s1, s0      :   in std_logic;
        x           :   out std_logic
  );
end mux_when_else; 

architecture arch of mux_when_else is
    signal sel : std_logic_vector (1 downto 0);
begin
    sel <= s1 & s0;
    x <= a when sel="00" else
         b when sel="01" else
         c when sel="10" else
         d;
end arch;

library ieee;
use ieee.std_logic_1164.all;

entity mux_with_select is
  port(
        a, b, c, d  :   in std_logic;
        s1, s0      :   in std_logic;
        x           :   out std_logic
  );
end mux_with_select; 

architecture arch of mux_with_select is
    signal sel : std_logic_vector (1 downto 0);
begin
    sel <= s1 & s0;
    with sel select
        x <= a when "00",
             b when "01",
             c when "10",
             d when others;
end arch;